Monopoly Power: Use, Proof, and Relationship to Anticompetitive

Monopoly Power: Use, Proof, and Relationship to Anticompetitive

42 Pages · 2008 · 136 KB · English

*The views expressed are those of the author and Policy Studies’ staff and do not necessarily reflect the views of the Commission or any individual Commissioner.

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Fault model1 Fault Modeling Some Definitions Why Modeling Faults Various Fault Models Fault Detection Fault Collapsing (Source: NCTU  ) Fault model2 Some Real Defects in Chips Processing Faults – missing contact windows – parasitic transistors – oxide breakdown Material Defects – bulk defects (cracks, crystal imperfections) – surface impurities (ion migration) TimeDependent Failures – dielectric breakdown – electromigration Packaging Failures – contact degradation – seal leaks Fault model3 Faults, Errors and Failures Fault: A physical defect within a circuit or a system – May or may not cause a system failure Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states – Caused by faults Failure: Deviation of a circuit or system from its specified behavior – Fails to do what it should do – Caused by an error Fault > Error > Failure Fault model4 Why Model Faults ? Fault model identifies target faults –Model faults most likely to occur Fault model limits the scope of test generation –Create tests only for the modeled faults Fault model makes effectiveness measurable by experiments –Fault coverage can be computed for specific test patterns to reflect its effectiveness Fault model makes analysis possible –Associate specific defects with specific test patterns Fault model5 Fault Models  StuckAt Faults  Bridging Faults  Transistor StuckOn/Open Faults  Functional Faults  Memory Faults  PLA Faults  Delay Faults  State Transition Faults Fault model6 Single StuckAt Faults 0 1 1 10 1/0 1/ 0 stuckat0Faultfree Response Test Vector Faulty Response Assumptions:  Only one line is faulty  Faulty line permanently set to 0 or 1  Fault can be at an input or output of a gate Fault model7 Multiple StuckAt Faults Several stuckat faults occur at the same time –Important in high density circuits For a circuit with k lines –there are 2k single stuckat faults –there are 3 k1 multiple stuckat faults Fault model8 Why Single StuckAt Fault Model?  Complexity is greatly reduced Many different physical defects may be modeled by the same logical single stuckat fault  Single stuckat fault is technology independent Can be applied to TTL, ECL, CMOS, etc  Single stuckat fault is design style independent Gate Arrays, Standard Cell, Custom VLSI  Even when single stuckat fault does not accurately model some physical defects, the tests derived for logic faults are still valid for most defects  Single stuckat tests cover a large percentage of multiple stuckat faults Fault model9 Bridging Faults A B f g A B f g A Bf g A Bf g Two or more normally distinct points (lines) are shorted together –Logic effect depends on technology –WiredAND for TTL –WiredOR for ECL –CMOS ? Fault model10 CMOS Transistor StuckON 0 stuckon ? IDDQ  Transistor stuckon may cause ambiguous logic level  When input is low, both P and N transistors are conducting causing increased quiescent current, called IDDQ fault – depends on the relative impedances of the pullup & pulldown networks Fault model11 CMOS Transistor StuckOPEN 0 stuckopen ? = previous state  Transistor stuckopen may cause output floating Fault model12 CMOS Transistor StuckOPEN (Cont) 10 stuckopen 01/00 Initialization vector memory behaviour  Can turn the circuit into a sequential one  Stuckopen faults require twovector tests Fault model13 Functional Faults  Fault effects modeled at a higher level than logic for function modules, such as Decoders Multiplexers Adders Counters RAMs ROMs Fault model14 Functional Faults of Decoder f(L i/L j): Instead of line L i, Line L j is selected f(L i/L i+L j ): In addition to L i, L j is selected f(L i/0): None of the lines are selected 2bit Decoder A B AB AB AB AB Fault model15 Memory Faults Parametric Faults –Output Levels –Power Consumption –Noise Margin –Data Retention Time Functional Faults –Stuck Faults in Address Register, Data Register, and Address Decoder –Cell Stuck Faults –Adjacent Cell Coupling Faults –PatternSensitive Faults Fault model16 Memory Faults (Cont) Patternsensitive faults: the presence of a faulty signal depends on the signal values of the nearby points –Most common in DRAMs Adjacent cell coupling faults –Pattern sensitivity between a pair of cells0 0 0 0 d b 0 a 0 a=b=0 d=0 a=b=1 d=1 Fault model17 PLA Faults  Stuck Faults  Crosspoint Faults Extra/Missing Transistors  Bridging Faults  Break Faults Fault model18 Missing Crosspoint Faults in PLA A B C f1 f2 ABC f1 f2 Growth Disappearance sa1 sa0  Missing crosspoint in ANDarray Growth fault  Missing crosspoint in ORarray Disappearance fault Equivalent stuck fault representation Fault model19 Extra Crosspoint Faults in PLA  Extra crosspoint in ANDarray Shrinkage or disappearance fault  Extra crosspoint in ORarray Appearance fault Equivalent stuck fault representation A B C f1 f2 ABC f1 f2 Disapp "1" Shrinkage "0" Appearance Fault model20 GateDelayFault Slow to rise, slow

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